Search results for "Register-transfer level"
showing 4 items of 4 documents
FPGA-based embedded Logic Controllers
2014
In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be s…
Chairs' welcome message
2004
In this paper we present techniques for comparison between behavioral level and register transfer level (RTL) design descriptions by mapping the designs into virtual controllers and virtual datapaths. We also discuss about how the equivalence between behavioral level and RTL designs can be defined precisely using the proposed "attribute statements" in an interactive fashion. Implementation issues as well as considerations on real life industrial design examples are presented as well.
Optimal implementation of neural activation functions in programmable logic using fuzzy logic
2006
Abstract This work presents a methodology for implementing neural activation function in programmable logic using tools from fuzzy logic. This methodology will allow implementing these intrinsic non-linear functions using comparators and simple linear modellers, easily implemented in programmable logic. This work is particularized to the case of a hyperbolic tangent, the most common function in neural models, showing the excellent results yielded with the proposed approximation.
Co-simulation platform based on systemc for multiprocessor system on chip architecture exploration
2007
Currently multiprocessor embedded systems are the principal vectors of semiconductor industry. Modelling, validating and analyzing a system performances impose the evolution of the traditional simulation techniques. In this paper we define the methodology we used in constructing the STARSoC co-simulation environment. This platform aims to explore at higher levels of abstractions a multiprocessors system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. Our purpose is to develop a complete design space exploration tool. In order to ass…